library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity EdgeDetector is
  port (Sig : in std_logic;
        Clk : in std_logic;
        FallingEdge : out std_logic;
        RisingEdge : out std_logic);
end EdgeDetector;

architecture beh of EdgeDetector is

  signal edge : std_logic_vector(1 downto 0):="00";
  signal prev,fall,rise : std_logic:='0';

begin
  
  FallingEdge<=fall;
  RisingEdge<=rise;  
  
  process(Sig,Clk)
  begin
    if rising_edge(Clk) then
	    edge<=edge(0) & Sig;
		  if edge = "00" and prev = '1' then
		    fall <= '1';
   		   rise<='0';
		    prev<='0';
    		elsif edge = "11" and prev = '0' then
    		  prev<='1';
		    fall<='0';
     	  rise<='1';
     	else
		    fall<='0';
		    rise<='0';
    		end if;
  	 end if;
  end process;
  
end beh;